I’ve not actually written anything here for quite some time (it turns out that doing a part-time PhD really eats into your electronics project time… Who’d’ve thought!); so I thought I’d take advantage of the current isolation and a few days off over the Bank Holiday, to catch-up with some blogging…
The venerable NE555 timer IC was introduced in 1972; and due to its versatility is without doubt one of the most common integrated circuits ever made.
The Three Fives kit
As a Christmas gift, I received a EvilMadScientist.com “Three Fives” kit. The three fives, is a giant-sized recreation of the NE555, build using through-hole discrete components.
I finally got around to building it, and since I have to say that it’s a really nice kit; and it would make a great electronics project for kids (aged about 12-18) too. It’s a really well laid-out board; and the use of through-hole components makes it easy to assemble. It took me about 45-minutes to solder it – but you could easily do it in more like 30-minutes, if you were less fussy about how it looked; and it might take you anything up to a couple of hours if you’d never soldered before… The instructions are very clear; and the components are supplied fixed on to clearly marked cards, to make it trivial to identify which goes where.
To add the finishing touches, there’s a set of screw-terminals corresponding to each of the pins of the chip; and a set of legs, to give the board the appearance of a giant-sized DIP-8 IC.
Once completed, you have a fully working 555; which you can substitute for the real-thing in pretty much any example circuit you’d care to build.
I tested mine by building a simple astable oscillator… Very similar to the one I built some years ago for another blog post.
(Strictly speaking there should also be a 10nF capacitor between the control pin and ground; but for a simple example you can omit it, and it’ll still work).
As you can see from the photos – it worked well.
Not really having anything useful to do with a giant 555 timer IC, I decided to remove the legs, and frame it on my wall – as a rather geeky object d’art.
More about the 555 timer
Despite not having much to do with mine, the NE555 is actually a fascinating little chip – and the way that this kit is laid out clearly shows the internal blocks of the circuit (although disappointingly, for me at least, it doesn’t really clearly how they’re linked or connected). Of course, that’s nothing that a quick look at the data sheet for the 555 won’t tell us; and maybe there’s not room to do it clearly on the PCB (and let’s be honest, this almost certainly aimed at kids, and not geeks!).
Anyway, the block diagram looks something like this. As we can see, there are two comparators, an S/R Flip Flop & a set of resistors forming a voltage divider.
The combination of these can be used to create either an oscillator (such as in my example), a monostable timer (which I hope is still used as a great practical example in schools); or a bistable flip-flop.
Concentrating just on the oscillator; let’s see how it works in practice in a circuit.
The first thing to note is that those three identical resistors, create a classic voltage divider. Unless modified by an input on the control pin, the voltage on the negative input to the first comparator (the threshold comparator)will be ⅔ Vcc (so if we’re using a 5V supply – it’ll be 3.3V); meaning that for this to turn on (have a high output; and thus “setting” the S/R flip-flop), the input on pin 6 (the threshold) must be greater than this. Similarly the positive input to the second comparator (the trigger comparator) is ⅓ Vcc (so again, on a 5V supply, that’d be 1.6V); so for this to turn on (“resetting” the flip-flop), we need a voltage on the trigger input of less than this.
So if we’re not using the control input (and most simple examples don’t) – we can now change the digital state of output simply by varying the (analogue) voltages on the two input pins 2 & 6.
So let’s look at the example circuit again.
As you can see we tie these two input together (which amongst other things prevents them ever being in a state which causes both comparators to turn on at the same time – creating an undefined condition in the S/R flip-flip). The output pin is pretty self-explanatory (although note that it uses an inverted output from the not-Q output of the flip-flop); and the reset pin (4) is tied to Vcc to prevent the chip resetting. This just leaves the discharge pin (pin 7) – and this, for our oscillator, is where the clever bit happens.
We connect discharge to Vcc via the first of our external resistors (R1); and to the threshold & trigger pins, via the second (R2). We then also connect both of those pins to ground via our capacitor. The values that we select for these three components, will determine both the frequency of the oscillator, and the duty-cycle: but we’ll come back to this in a moment.
To output a high signal on the output pin – we need to set the state of the R/S flip-flop: and as we saw earlier we do this by pulling the trigger lower than ⅓ of Vcc. So when we start the oscillator running, pin two is pulled low: until the capacitor is charged above ⅔ Vcc. The time required for this capacitor to reach this voltage depends on the capacitance and the resistance of the combined series-resistance of the R1 + R2.
The comparator connected to the trigger pin will have switched off, as the voltage passed ⅓ Vcc – but R/S flip-flop stays “set” (and the output stays high); but once the voltage gets to above the ⅔ Vcc feeding the threshold comparator will turn on, resetting (or clearing) the flip-flop. This obviously turns the output off; but it also effects the transistor also on the not-Q output of the flip-flop – and it’s this, that permits the circuit to oscillate.
As soon as not-Q goes high, it turns on the transistor, creating a path to ground to discharge the capacitor, through R2…
As the capacitor discharges, it’ll initially pass the ⅔ Vcc threshold (turning off the threshold comparator, and thus clearing the reset signal to the S/R flip-flop); and then eventually, it’ll drop below ⅓ Vcc, and will thus turn on the trigger comparator again, taking us back to where we started – as the flip-flop “sets” turning off the transistor, turning on the output, and starting the process of charging the capacitor all over again.
This really is a beautifully simple circuit.
I said I’d come back to the question of the duty cycle and frequency. As you can probably see yourself – the frequency is controlled by the sum of R1+R2, and the capacitance. The more that we increase any of these, the longer it will take for the capacitor to charge (or discharge) to the relevant threshold, and so the lower the frequency.
But let’s look at this in a little more detail.
To calculate the time (t) taken for a simple resistor-capacitor (RC) circuit to reach a given voltage (Vc), with a supply voltage of V: we us the formula:
If we want to calculate the time that the time the output will be high, then this is the same as calculating the time to charge the capacitor from its initiate state of ⅓ Vcc to our target threshold of ⅔ Vcc.
To do this, we simply equate supply voltage (V) with respect to the capacitor as being:
(e.g. the difference in the potential is ⅔ of Vcc); and our target voltage Vc is:
From here we can easily calculate the rest…
For discharging we use basically the same formula – except that this time the formula is simpler – since we only need to worry about discharging from an initial state (V) to our target state (Vc)…
We can then do the same thing for the discharge – noting that this time we only use the resistance value of R2 (since R1 isn’t used when discharging).
The total time required for each of these operations to occur – equals the cycle time:
And thus the frequency (F) is the reciprocal of this:
So for our demo circuit (where R1 = 100KΩ, R2= 100KΩ, and C = 4.2µF); we can calculate that:
This compares pretty well with the observed value…
Lastly there just remains the question of calculating the duty cycle. This is just:
Or to expand:
which in our example is:
Again we can see the this matches our experimental result.
The one consequence of the way the duty cycle is determined is that we can never quite hit 50% (or less). The closest we can ever get is by making R1 very small in comparison with R2 (e.g. 100Ω & 3.6MΩ with a 1nF capacitor – would give you a 2KHz output with a duty cycle of 50.07%); but that’s close enough for most applications.